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Design Analysis Template

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Figure 1: Board Example

ANALYSIS DESCRIPTION NAME

Notes: A generalized name for this description: e.g., Structural Test Post-Assembly.

ANALYSIS DESCRIPTION IDENTIFIER

Notes: A simple single identifier that may be referenced instead of the entire name: e.g., STPA001.

OPERATION OVERVIEW BEING ANALYZED

Notes: This section provides a high level description of the operation being performed on the board that this analysis is targeting to allow the reader to understand the motivation for why this operation is necessary for this particular use case and product life cycle state.

DESIGN TARGETED

Notes: A reference to the design diagram being targeted for this analysis.

USE CASE TARGETED

Notes: This section describes the particular SJTAG Use Case targeted by this analysis. The analysis description should focus specifically on what needs to be done with the board in order to be able to perform this operation. Delete as required from the following list:
  • Structural Test (ST)
  • Configuration / Tuning / Instrumentation (CTI)
  • Software Debug (SD)
  • Built-In Self Test (BIST)
  • Fault Injection (FI)
  • Programming / Updates (PU)
  • Root Cause Analysis / Failure Mode Analysis (RCA/FMA)
  • Power-on Self Test (POST)
  • Environmental Stress Test (EST)
  • Device Versioning (DV)

PRODUCT LIFE CYCLE STAGE ADDRESSED

Notes: This section describes the specific product life cycle being addressed by this analysis. For example, Post-assembly Manufacturing Test. Delete as required from the following list:
  • Post-assembly Manufacturing Test
  • More items need defined for this list

INHERITANCE

Notes: List of other Analysis Descriptions this description extends by adding features to the previous descriptions to reduce the amount of common descriptions captured during previous work.

ASSUMPTIONS

Notes: This section captures in free form text the assumptions that have to be made during the operations on this board to enable and support this use case.

DEPENDENCIES

Notes: This section captures in free form text the dependencies that are external to this particular use case and product life cycle. For example, a dependency may be a shorts test of the power pins is required prior to this operation being performed on the board. Another example may be the dependency that all programmable devices need to be in an erased state before this operation could be performed.

OPERATIONAL LEVEL REQUIRED

Notes: TBD
Brad's note: I was trying to capture Harrison’s product state here. Not sure if this belongs in the DEPENDENCIES section above instead.

[Delete as required from the following list:]

  • Out of Service
  • More items need defined for this list

JTAG TECHNIQUES USED

Notes: This section captures the test techniques that are going to be applied to the board during this operation. Suggested techniques are: IEEE 1149.1 interconnect testing (list block identifiers from diagram), IEEE 1149.6 interconnect testing (list block identifiers from diagram), IEEE 1149.1 based cluster testing of (list block identifiers from diagram), IEEE 1149.1 based programming of (list block identifiers from diagram), FPGA-based-instrument testing of (list block identifiers from diagram), FPGA-based-instrument programming of (list block identifiers from diagram), etc.
  • IEEE 1149.1 interconnect testing (list block identifiers from diagram)
    • Access to boundary-scan register of U3 in EXTEST mode (add purpose and block identifiers from diagram)
  • IEEE 1149.6 interconnect testing (list block identifiers from diagram)
  • IEEE 1149.1 based cluster testing of (list block identifiers from diagram)
  • IEEE 1149.1 based programming of (list block identifiers from diagram)
  • FPGA-based-instrument testing of (list block identifiers from diagram)
  • FPGA-based-instrument programming of (list block identifiers from diagram)
  • More items need defined for this list

TEST ACCESS POINT

Notes: This section captures the intended test access port on the design to be used to perform the operations described by this description. For example, the Primary Multi-drop interface of the GATEWAY. Another example would be the uP controlled TAP Controller. A third example would be the BIST Engine.

TEST CONFIGURATION REQUIRED

Notes: This section would describe the configuration required for the SELECTOR scan chains to be able to perform the operations described by this description.

CONSEQUENCES

Notes: Advantages and disadvantages in using this template.

SIMILAR DESCRIPTIONS

Notes: Used to capture a reference to the descriptions pertaining to other use cases or product life cycles where similar operations are taking place with this design.

SIBLING DESCRIPTIONS

Notes: Used to capture a reference to the descriptions pertaining to the same design and use case, but the specialization is different due to a different configuration or technique.