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Access Link 
A link (bus or discretes signals) that is used to configure the path used by a Data Link.
Application Specific Integrated Circuit (ASIC) 
A custom or semi-custom device designed to fulfil the requirements of a defined application. Unlike CPLDs or FPGAs, ASICs are foundry programmed and cannot be re-programmed by the user.


Board Level Self-Test (BLST) 
A form of BIT or BIST specifically targeting the functionality of the board in which the BLST resides.
Bottom-up Approach 
(SJTAG strategy) A strategy where each individual element (bottom) of a system determines its own configuration (state)/actions, based on its functional, behavioral, and performance requirements, to which its capabilities may be assembled by higher levels of a system architecture to provide the global configuration (state)/actions for a system.
Boundary-Scan (BScan)
The use of a serial scan-shift register called the Boundary-Scan Register (BSR) to provide controllability and observability of device I/O pins.
Boundary Scan Description Language (BSDL) 
Incorporated into the Boundary Scan standards as IEEE std 1149.1b in 1994, BSDL is a subset of VHDL (VHSIC Hardware Description Language) that describes how IEEE 1149.1 is implemented within a device and how it operates. Most vendors of BScan capable devices freely provide BSDL files for their products, and most BScan software tools can import BSDL files.
Boundary Scan Enhanced (BSE) 
e.g. "Boundary Scan Enhanced POST" or "BSE POST", refers to the addition of boundary scan to some established activity in order to complement or extend the capabilities of that activity.
Built-In Self-Test (BIST) 
BIST is a method of design-generally for ICs-whereby the mission circuit tests itself. Though this is seldom performed strictly without additional circuitry, if the entire circuitry performing the test is contained within an IC, we call it self-test, in situ test, or built-in self-test. (A proposed definition from the Testability Management Action Group)
Built-In Test (BIT) 
Similar to BIST in that it performs test of the circuit it resides in, but it is generally used at board and system levels and often uses extra hardware, software, and/or firmware to implement the test. When the added circuitry is substantial, it may be called embedded test. If BIT is implemented in software, it is called BIT software. (A proposed definition from the Testability Management Action Group)
A single-bit register applied in parallel to the BSR that reduces the device’s scan shift-path to only 1 bit.


Capture-Shift-Update (CSU) 
The sequence of operations applied to a test data register (TDR) to capture new data from the data-input port, shift the data through the TDR, then update the newly shifted data into the update stage of the TDR.
Complex Programmable Logic Device (CPLD) 
CPLDs are a class of programmable logic devices. They feature the speed, design simplicity, and predictability of PALs. Conceptually, they consist of PAL-like function blocks that can be interconnected through a switch matrix.


Data Link 
A link used to transfer test data (applied vectors or results) between the Test Controller and the device(s) involved in the test, adhering to the Capture/Shift/Update flow. There may be more than one data link per device in the SJTAG domain and data links may be unidirectional or bidirectional.
Diagnose, Diagnosing 
An activity in pursuit of diagnosis.
Diagnostic Tests 
Tests intended to determine the cause of a possible malfunction and to suggest a repair strategy.
The process of identifying or determining the root cause of a set of test results or observations that are indicative of a malfunction.
The set of conclusions drawn from diagnostics.
The use of the Select-DR Scan side of the 1149.1 State-Machine – this action is associated with accessing and using a targeted TDR.


Embedded Boundary Scan Test (EBST) 
Embedded BST means that an Embedded Test Controller based on an available processor located within the UUT becomes responsible for executing test and configuration operations. The controller uses a UUT resident application and associated test data for stimulation or configuration of the devices within the UUT and for evaluation or verification of responses from the UUT.
Embedded Test Controller (ETC) 
If some, or all of the functionality of a runtime-control Test Manager is built into the UUT, then this is referred to as an Embedded Test Controller (ETC), and defined to be the combination of an on-board host microprocessor plus, if needed, a special device called a JTAG Protocol Manager (JTAG-PM).
EXternal Boundary Scan Test (XBST) 
Conventional eXternal BST is carried out by applying test stimuli or configuration data to the UUT from some external source under the control of an external Test Manager and evaluating the results by observing the response from the UUT and comparing with expected results back at the external Test Manager.


Field Replaceable Unit (FRU) 
At field service, an FRU is the level of sub-assembly that would normally be exchanged to effect a repair, the FRU subsequently being returned to a service depot for repair. Equivalent terms, for the purposes of SJTAG discussions, may include LRU (Line Replaceable Unit) and SRI (Shop Replaceable Item).
Field Programmable Gate Array (FPGA) 
FPGAs are a class of programmable logic devices. They feature a gate-array-like architecture with a matrix of logic cells surrounded by a periphery of I/O cells.


A device used as part of a chain selection mechanism and that provides an interface to the upstream topology, typically to selectively provide access to the scan chain(s) of a board from a multi-drop bus.
General-purpose Native jtAg Tester (GNAT) 
An instrumentation port developed by Silicon and Software Systems to provide access to User Data Registers through the 1149.1 TAP on Xilinx FPGAs.


Hierarchical Instrument 
An instrument that also provides a hierarchical connection by passing on, at a minimum, the Select-Instrument signal and the TDI-TDO serial scan-path which may be referred to, using the IEEE 1500 nomenclature, as the WSI-WSO serial scan-path to distinguish it from the serial scan path in the 1149.1-Zone. Basically, a Hierarchical Instrument provides access to other instruments that do not require a direct IR-Scan.


(General) A device or feature within a device that provides a capability for monitoring or control, e.g. monitoring of device temperature or tuning of a SERDES link. See also Hierarchical Instrument.
(IEEE 1687) Any on-chip circuit for test, debug, diagnosis, monitoring, characterization, configuration, or functional use that can be accessed by, configured from, or communicated with by an on-chip network described in Instrument Connectivity Language (ICL) that connects to an external device interface. An instrument is typically in a module that has only a client interface.
The use of the Select-IR Scan side of the 1149.1 State-Machine – this action is associated with accessing the 1149.1 Instruction Register.


JTAG Capture-Shift-Update 
Three states in the 1149.1 State-Machine involved in a DR-Scan that drives BSR or TDR cells – or involved in an IRScan that drives the 1149.1 Instruction-Register – in direct association with their named actions: Capture allows the cell to observe a signal; Shift allows a cell to pass data from one cell to another cell through a serial shift path; and Update allows a cell to transfer data from the shift path to the parallel output of the cell – this sequence of events is the fundamental basis for how 1149.1 operates. This is a specialization of the generic Capture-Shift-Update flow.
JTAG Switch Module (JSM) 
A multiplexing switch, allowing a single Test Access Port to be used to operate one of a number of scan chains.
The acronym for the Joint Test Action Group - the group identity used by the original creators of the 1149.1 standard. JTAG is often used to mean the 1149.1 standard itself rather than the group of originators.
JTAG Protocol Manager (JTAG-PM) 
This is the hardware interface between the microprocessor and the boundary-scan infrastructure on the board, delivering and receiving the low-level JTAG protocol signals and responses.




Master Test Controller (MTC) 
In a system where the control and execution of test functions may be delegated to multiple embedded Test Controllers, e.g. for parallelism, a Master Test Controller will coordinate the activities of all the Test Controllers in the system. The MTC may be either external or embedded.
Multi-Drop Configuration 
A topology for connecting the IEEE 1149.1 Test Access Ports of the boards within a system where all the TAP signals are bussed to each of the boards. This architecture requires some additional method to select which board is being addressed.




Project Authorization Request (PAR) 
A document submitted to the IEEE Standards Board requesting authority to produce a new standard or to amend an existing standard.
Protocol Adapter 
A module used to transform test data and control between the interface protocol used on the controlling side and the interface protocol used on the target side of the adapter. A Protocol Adapter may be instantiated either as hardware logic or as a software module.
Public Instructions 
A set of instructions defined in the 1149.1 Standard as being required or optional, but that are fully defined in their operation and the registers they access – the ten public instructions are: EXTEST, SAMPLE, PRELOAD, BYPASS (all mandatory), INTEST, RUNBIST, IDCODE, USERCODE, CLAMP, and HIGHZ (all optional).



Radial Configuration 
See Star Configuration.
Ring Configuration 
A topology for connecting the IEEE 1149.1 Test Access Ports of the boards within a system where the TDO from one board feeds into the TDI of the next. Also known as Daisy Chain Configuration.
From the SJTAG perspective a Router is a generic term describing devices that offer the functionality of a Gateway and/or a Selector.


Scan Proxy 
The delegation by the Test Control System of the execution of scan operations (e.g. SVF or STAPL primitives) on a remote target outside of the current controller. See also Test Step Proxy and Vector Proxy.
SJTAG Control System 
A term used to describe any combined hardware/software entity that provides control of the execution of some part of the SJTAG application. Multiple SJTAG Control Systems may exist and responsibility may be delegated from one to another in a hierarchical manner. See also SJTAG Manager.
SJTAG Manager 
A term used to describe any combined hardware/software SJTAG Control System that is used as a free-standing or integral on-line runtime controller providing top-level management of UUT test or configuration operations.

TBD: Differentiate between development and execution cases.

Star Configuration 
A topology for connecting the IEEE 1149.1 Test Access Ports of the boards within a system where each board has it's own dedicated test bus. Typically a JSM will be used to select which bus is in use.
A device which provides an interface to the downstream scan chain(s) and links one or more scan chains into a chain accessible by the SJTAG Control System.
A noted sub-operation of DR-Scan that represents the action of shifting data through the defined serial scan-path that is connected between the device’s TDI-TDO when the 1149.1 State Machine is in the Shift-DR state.
For the purposes of SJTAG, a system may be described as an organized collection of components or assemblies that are designed to operate together to perform one or more tasks or functions.


An 1149.1 dedicated signal, the Test-Clock that synchronizes all 1149.1 actions.
1149.1 dedicated signal, the Test-Data-Input that is the beginning of the device’s 1149.1 serial scan-path.
The abbreviation for the 1149.1 serial scan-path inside a device from the device’s TDI pin to the device’s TDO pin via either the 1149.1-IR or any one of a variety of 1149.1-TDRs.
An 1149.1 dedicated signal, the Test-Data-Output that is the end of the device’s 1149.1 serial scan-path.
The abbreviation for the Test-Data-Register – any serial shift-register that operates in accordance with the 1149.1 DR-Scan sequence.
Test Access Mechanism (TAM) 
The connectivity and protocol structure used to access an instrument. For IEEE Std 1500, a defined TAM exists.
Test Access Port (TAP)
A serial data interface defined by IEEE std 1149.1, consisting of four mandatory signals, Test Data In (TDI), Test Data Out (TDO), Test Mode Select (TMS), Test Clock (TCK) and one optional signal, Test Reset (TRST*). This term may be used in reference to the physical connections of either a device, board or system .
Test Step 
The smallest unit of a testing sequence that can produce a test result.
Test Step Proxy 
The delegation by the SJTAG Control System of the execution of test step operations on a remote target outside of the current controller. See also Scan Proxy and Vector Proxy.
A property of a circuit that enables it to be tested easily, or in some cases, to be tested at all, by being able to control and observe signal nodes that are buried within the circuit. (A proposed definition from the Testability Management Action Group)
Testability Partitioning 
The grouping of tests based on all having common dependencies.
The acronym for the Test-Logic-Reset state in the 1149.1 State-Machine – entering this state places all 1149.1 logic into an inert reset state.
An 1149.1 dedicated signal, the Test-Mode-Control that directs the state transitions of the 1149.1 State-Machine on the rising-edge of TCK.
Top-down Approach 
(SJTAG strategy) A strategy where the desired configuration (state)/actions of the system is determined by decomposing a system into its constituent parts and determining the set of configuration (state)/actions by analyzing the parts to determine the overall configuration (state)/actions of the system.
An 1149.1 dedicated signal, the active-low asynchronous Test-Reset signal.


A noted sub-operation of DR-Scan that represents the action of synchronizing all change actions of the target 1149.1 register or 1687 instrument that is active under the current selected instruction when the 1149.1-SM is in the Update-DR state at the falling-edge of TCK.


Vector Proxy 
The delegation by the Test Control System of the application of vectors to a remote target outside of the current controller. See also Scan Proxy and Test Step Proxy.


Wrapper-Boundary Register (WBR) 
An IEEE Std 1500 serial shift-register similar to the BSR of a device, but with more defined capabilities, that is meant to wrap around a core to provide the ability to test the core in isolation (in-facing mode), or the test logic attached to the core using the wrapper instead of the core (out-facing mode).
Wrapper-Bypass Register (WBY) 
A single-bit register applied in parallel to the IEEE Std 1500 registers (e.g. WIR, CDR, WDR) that can be used to reduce the Wrapper’s scan shift-path to only 1 bit.
Wrapper Instruction Register (WIR) 
The local instruction register associated with the IEEE Std 1500 TAM.
A IEEE Std 1500 TAM signal, Wrapper-Serial-Input, that is the beginning of the serial scan-path for the IEEE Std 1500 Test Wrapper.
The abbreviation for the IEEE Std 1500 serial scan-path, Wrapper-Serial-Input to Wrapper-Serial-Output.
A IEEE Std 1500 TAM signal, Wrapper-Serial-Output, that is the end of the serial scan-path for the IEEE Std 1500 Test Wrapper.


See External Boundary Scan Test.