GDPR, 2018: Please see the revised Pivacy Policy for this wiki: General Data Protection Regulation
EU Cookie Directive: Please see the following note regarding opting in to the use of cookies for this wiki: EU Cookie Directive

Please Note: You must be logged in to edit this wiki and your account must be assigned "editor" rights (set by administrator).

Glossary

From SJTAG
Revision as of 12:54, 1 July 2008 by Ian McIntosh (talk | contribs)
Jump to: navigation, search

Glossary


A

B

C

D

E

Embedded Boundary Scan Test (EBST) 
Embedded BST means that an Embedded Test Controller based on an available processor located within the UUT becomes responsible for executing test and configuration operations. The controller uses a UUT resident application and associated test data for stimulation or configuration of the devices within the UUT and for evaluation or verification of responses from the UUT.
ETC 
Embedded Test Controller. If some, or all of the functionality of a runtime-control Test Manager is built into the UUT, then this is referred to as an Embedded Test Controller (ETC), and defined to be the combination of an on-board host microprocessor plus, if needed, a special device called a JTAG Protocol Manager (JTAG-PM).
EXternal Boundary Scan Test (XBST) 
Conventional eXternal BST is carried out by applying test stimuli or configuration data to the UUT from some external source under the control of an external Test Manager and evaluating the results by observing the response from the UUT and comparing with expected results back at the external Test Manager.

F

FRU 
Field Replaceable Unit. At field service, an FRU is the level of sub-assembly that would normally be exchanged to effect a repair, the FRU subsequently being returned to a service depot for repair. Equivalent terms, for the purposes of SJTAG discussions, may include LRU (Line Replaceable Unit) and SRI (Shop Replaceable Item).

G

H

I

J

JSM 
JTAG Switch Module. A multiplexing switch, allowing a single Test Access Port to be used to operate one of a number of scan chains.
JTAG-PM 
JTAG Protocol Manager. This is the hardware interface between the microprocessor and the boundary-scan infrastructure on the board, delivering and receiving the low-level JTAG protocol signals and responses.

K

L

M

Multi-Drop Configuration 
A topology for connecting the IEEE 1149.1 Test Access Ports of the boards within a system where all the TAP signals are bussed to each of the boards. This architecture requires some additional method to select which board is being addressed.

N

O

P

PAR 
Project Authorization Request. A document submitted to the IEEE Standards Board requesting authority to produce a new standard or to amend an existing standard.

Q

R

Radial Configuration 
See Star Configuration.
Ring Configuration 
A topology for connecting the IEEE 1149.1 Test Access Ports of the boards within a system where the TDO from one board feeds into the TDI of the next. Also known as Daisy Chain Configuration.

S

Star Configuration 
A topology for connecting the IEEE 1149.1 Test Access Ports of the boards within a system where each board has it's own dedicated test bus. Typically a JSM will be used to select which bus is in use.

T

Test Manager 
A term used to describe any combined hardware/software test control system that is used either as a free-standing off-line test program developer and/or as a free-standing or integral on-line runtime controller for UUT test or configuration operations.

U

V

W

X

XBST 
See External Boundary Scan Test.

Y

Z