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Go/NoGo Instrumented Test of AC Coupled Links with One Device Tx and One Device Rx

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Figure 1: Board Example

ANALYSIS DESCRIPTION NAME

Go/NoGo Instrumented Test of AC Coupled Links with One Device Tx and One Device Rx

ANALYSIS DESCRIPTION IDENTIFIER

TBD

OPERATION OVERVIEW BEING ANALYZED

  • testing assembly connectivity for correctness, including placement, orientation, correct device, basic "aliveness", shorts and opens.
  • a table for the PCOLA/SOQ would be useful at this point, and should be part of the template.
  • focus is on detection of a failure, not diagnosis for the defect.
  • test based on predetermined AC pattern from U5 to U6 or vice versa (chip to chip).
  • intent is to confirm that a data eye can be established.

DESIGN TARGETED

  • U5/U6 circuit block.

USE CASE TARGETED

  • Structural Test (ST)

* Configuration / Tuning / Instrumentation (CTI)

  • Software Debug (SD)
  • Built-In Self Test (BIST)
  • Fault Injection (FI)
  • Programming / Updates (PU)
  • Root Cause Analysis / Failure Mode Analysis (RCA/FMA)
  • Power-on Self Test (POST)
  • Environmental Stress Test (EST)
  • Device Versioning (DV)

PRODUCT LIFE CYCLE STAGE ADDRESSED

  • Post-assembly Manufacturing Test
Harrison's note: Important aspect is that this is a case of reuse of something developed for NPI.

INHERITANCE

None yet.

ASSUMPTIONS

  • U7 addressing is properly configured to access U5 and U6.
  • Any compliance enable condition can be set from some boundary scan controlled IO port, e.g on U15 or U7.
  • power is supplied to the DSPs(U5, U6) and Bridge (U7), the Gateway (U12), and the Selector (U13); (could go under DEPENDENCIES)
  • Any ICE/debug port is not conflicting with boundary scan access.
  • Necessary instrumentation is provided either as soft core or hard core within the DSPs.
  • Instruments are controllable through the 1149.7 port on each DSP.
  • The state of the transmit, and receive instruments, including the lanes to be used, is known to and controlled by the Test Manager.
    • The state may be set through JTAG or some other interface (e.g. I2C, SPI, etc.) that is under the control of the Test Manager.

DEPENDENCIES

  • power pins have been tested for shorts prior to this test;
  • any 1149.1 compliance enable pins for U5 and U6 are controllable by the host tester (DFT requirement);
  • Scan chain is designed so that the selector has access to U7(DFT requirement);
  • Scan chain connectivity to U5, U6 and U7 has been verified prior to this test;

OPERATIONAL LEVEL REQUIRED

  • Out of Service

JTAG TECHNIQUES USED

  • IEEE 1149.6 interconnect testing (U5 and U6)
  • IEEE 1149.1-2013 (example C.5) interconnect testing using instrumentation IP (U5 and U6)

TEST ACCESS POINT

  • Gateway (U12), accessing U5 and U6 through the Selector (U13) and Bridge (U7).

TEST CONFIGURATION REQUIRED

  • Only needed scan chain for this particular test would be the one from the Selector to U7 (translating to U5 and U6), unless compliance enable or other constraints are controlled by boundary-scan devices in other chains

CONSEQUENCES

  • Can be used for AC coupled nets.
  • Supports testing of links at the board edge.
  • Requires a means of coordination between Rx and Tx instruments.
  • Diagnostics can be provided down to a single lane.

SIMILAR DESCRIPTIONS

None at present.

SIBLING DESCRIPTIONS

Go/NoGo Instrumented Test of AC Coupled Links with a Single Loopback at One End