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Go/NoGo Memory Structural Test based on boundary-scan access from Host

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Figure 1: Board Example

ANALYSIS DESCRIPTION NAME

Go-No/Go Memory Structural Test based on boundary-scan access from Host

ANALYSIS DESCRIPTION IDENTIFIER

…TBD

OPERATION OVERVIEW BEING ANALYZED

  • testing assembly connectivity for correctness, including placement, orientation, correct device, basic "aliveness", shorts and opens;
  • a table for the PCOLA/SOQ would be useful at this point, and should be part of the template;
  • focus is on detection of a failure, not diagnosis for the defect;
  • test is based on data persistence in the RAM, writing data to certain memory locations and then reading data back from the same memory locations, under control of the boundary-scan register of the Host (U3)
  • treatment of U1 and U2 as separated devices or not depends on how they are connected to the Host in terms of data bus width (are they both part of a wide data bus, or are they using the same data bus signals in a banked configuration);

DESIGN TARGETED

  • U1, U2, U3 circuit block

USE CASE TARGETED

  • Structural Test
    • (perhaps add a cross reference to the respective Use Case wiki entry)

  • Configuration / Tuning / Instrumentation (CTI)
  • Software Debug (SD)
  • Built-In Self Test (BIST)
  • Fault Injection (FI)
  • Programming / Updates (PU)
  • Root Cause Analysis / Failure Mode Analysis (RCA/FMA)
  • Power-on Self Test (POST)
  • Environmental Stress Test (EST)
  • Device Versioning (DV)

PRODUCT LIFE CYCLE STAGE ADDRESSED

  • Post-assembly Manufacturing Test
  • Brad noted that both the Use Case Targeted section and this section would be good candidates for a list of check boxes

INHERITANCE

  • none yet

ASSUMPTIONS

  • in this case, if Flash device U4 shares the same data bus as U1 and U2, U4 needs to be kept inactive during the test of U1 and U2; so, the assumption would be that U4 can be disabled during the test;
  • U3 needs to have boundary-scan access to control U1 and U2, and any compliance enable conditions must be met;
  • clock on synchronous memory devices can be controlled with boundary-scan access;
  • memory has to be able to retain the test data for the amount of time needed to read them back with boundary-scan access;
  • power is supplied to the memories (U1, U2) and Host (U3), the Gateway (U12), and the Selector (U13); (could go under DEPENDENCIES)
  • we are allowed to disrupt the data that may reside in the memory prior to the test;
  • Any ICE/debug port is not conflicting with boundary scan access.

DEPENDENCIES

  • power pins have been tested for shorts prior to this test;
  • any 1149.1 compliance enable pins for U3 are controllable by the host tester (DFT requirement);
  • Scan chain is designed so that the selector has access to U3 (DFT requirement);
  • Scan chain connectivity to U3 has been verified prior to this test;

OPERATION LEVEL REQUIRED

  • Brad thinks that this could be the operational state of the circuit card;
  • since this is a "destructive" test of the state of the board, the operational level would be "out of service";

JTAG TECHNIQUES USED

  • IEEE 1149.1;
  • access to boundary-scan register of U3 in EXTEST mode to control all address, data, and control signals on U1 and U2;

TEST ACCESS POINT

  • Gateway (U12), accessing U3 through the Selector (U13);

TEST CONFIGURATION REQUIRED

  • only needed scan chain for this particular test would be the one from the Selector to U3, unless compliance enable or other constraints are controlled by boundary-scan devices in other chains;

CONSEQUENCES

  • TBD

SIMILAR DESCRIPTIONS

  • none yet

SIBLING DESCRIPTIONS

  • none yet