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Volume 1

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Volume 1 - Overview Document


About this Document

This document, Volume 1 of 5 volumes, provides an introductory overview of the objectives and defining principles of System-Level JTAG (SJTAG). The document is intended for those readers who are either either new to SJTAG or who only require a basic understanding of the application of SJTAG. It is assumed, however, that the reader has basic knowledge of the principles of JTAG Boundary Scan Test as described by IEEE 1149.1-2001, “IEEE Standard Test Access Port and Boundary Scan Architecture”.

Documentation Map

Readers seeking further information on specific topics are directed to the following volumes:

Scope of SJTAG

A “system”, for the purposes of SJTAG, is any hierarchical aggregation of inter-related and interconnected electronic circuits, the operation of which is sufficiently self-contained that it may be perceived as a single unit. From the end-user perspective, this means that a circuit board carrying a mezzanine daughter board may be considered a system, just as equally as the network of discrete electronic control modules within an automobile may be.

Since SJTAG is a development of JTAG (IEEE Std 1149.1), there is a presumption that the target system will have a significant digital content, and that the concept of applying JTAG at the individual circuit board level will already have been embraced.

By taking account of the special factors that arise when creating an assembly of circuit boards, and applying the corresponding SJTAG design principles to address those factors, then the underlying board level JTAG feature can be leveraged at the system level, creating a test access mechanism that extends the usefulness of JTAG throughout the entire product life-cycle: This is illustrated in the Venn Diagram of Figure 1: The SJTAG Universe.

File:SJTAG Universe.png
Figure 1: The SJTAG Universe

It is likely that users will identify additional applications areas for SJTAG not included in the diagram: The important point to take from Figure 1 is that the application potential of SJTAG extends significantly beyond the traditional board-level scope of structural test and device programming.

Purpose of SJTAG

The JTAG Background

When the Joint Test Action Group was formed in the late 1980s, it was in response to concerns over the reduction in board test access offered by new device packaging options and board construction techniques: JTAG was born out of the necessity to recover the testability that was being lost due to the use of these higher density board designs.

However, system level test access has always been relatively poor, due to the “closed” nature of the system itself. Access is largely limited to only those signals that form the mission interfaces of the system or that have been explicitly brought out to test connectors by the designer. This limited test access has been accepted by manufacturers as “normal”: There was no apparent reduction in test access that paralleled the board test scenario to instigate an improvement initiative. As systems have grown more complex, diagnosis of faults, or indeed confirmation of functionality, has become increasingly reliant upon the built-in test features of the system and it's constituent boards.

SJTAG identifies that not only can system test access, and therefore diagnostic accuracy, be greatly improved, but once that access is provided, other potential applications become accessible, increasing the value that can be realized from the employment of JTAG within the system design.

Primary Constraints

Open Standard

Device Independence


Tool vendor independence

Text here.

IEEE Std 1149.1 Based


Relationship to Other Standards

IEEE Standards

IEEE Std 1149.1-2001, “IEEE Standard Test Access Port and Boundary Scan Architecture”


IEEE Std 1149.4-1999, “IEEE Standard for a Mixed-Signal Test Bus”


IEEE Std 1149.6-2003, “IEEE Standard for Boundary-Scan Testing of Advanced Digital Networks”


IEEE Std 1532-2002, “IEEE Standard for In-System Configuration of Programmable Devices”


Industry Standards

Are there any???

Standards in Development

IEEE P1149.7 “Standard for Reduced-pin and Enhanced-functionality Test Access Port and Boundary Scan Architecture”


IEEE P1581 “Static Component Interconnection Test Protocol and Architecture”


IEEE P1687 (IJTAG) “Standard for Access and Control of Instrumentation Embedded within a Semiconductor Device”

Text Here.